基于自动测试生成的寄存器分配算法

Register assignment algorithm targeting automatic test pattern generation

提出了在寄存器分配时考虑可测性的一个新算法。它采用前向 /后向算法 ,将一个已调度好的 CDFG (ControlData Flow Graph)中的变量分配到相应的寄存器。通过对变量生命时间定义的扩展 ,本算法可以对带反馈的电路进行处理。在定义变量之间的寄存器复用相关函数时同时考虑了 3个准则 ,达到提高设计可测性的目的。

Since testing is often a design bottleneck, this paper presents an algorithm to consider testability during high level synthesis. Using the input control data flow graph for a design, the proposed algorithm binds each variable to a corresponding register using the left/right algorithm. The algorithm can deal with cyclic CDFG by the extension of variable lifetime. Three heuristics are used to direct the definition of sharing preference between variables to incorporate testability facts in register assignment. Finally, experimental results show that the algorithm can improve the testability of final designs.