应用于数字下变频中CORDIC算法的FPGA实现

FPGA implementation of CORDIC algorithm applied to digital down conversion

正余弦信号在GNSS接收终端的数字下变频中有着重要的应用,CORDIC算法是实现正余弦信号的最重要方法。立足于DDS与CORDIC算法的基本原理,针对CORDIC算法实现主要存在的3个问题,结合变象限法、流水线技术及相幅量化数据格式,在FPGA上通过实现CORDIC算法可在一个时钟周期内计算出正余弦信号幅值。仿真结果表明:与传统CORDIC算法实现相比,本文实现的正余弦信号精度高且速度快,并能满足GNSS接收终端数字下变频对正余弦信号的需求。

The sine and cosine signals are used in digital down conversion of GNSS receiver with important sense and the CORDIC algorithm is the most important way to implement the sine and cosine signals. According to the basic principle of DDS and CORDIC algorithm, aiming at the three existing problems in implementation of CORDIC algorithm, and combining the variable quadrant method, pipeline structure technique and phase/amplitude quantization data format, we have realized the CORDIC algorithm with FPGA and thus the amplitude values of sine and cosine signals can be calculated in one clock cycle. The simulation results show that compared with the traditional CORDIC algorithm implementation the implementation presented in this paper is characteristic of a higher accuracy of the sine and cosine signals and a higher speed, meeting the needs of the digital down conversion of GNSS receiving terminal.