JPEG2000中高性能Tier-1编码器的VLSI结构设计与实现

The VLSI Design and Implementation for High-performance Tier-1 Encoder in JPEG2000

为满足JPEG2000编码器的硬件实现需求,针对其中最为复杂和耗时的Tier-1编码器,提出了一种高效的硬件实现结构.该结构采用通道并行的位平面编码器,并且在通道内部采用基于列的点跳跃算法,提升了位平面的编码速度.同时,MQ编码器与位平面编码器配合,引入5级动态流水结构,进一步提高编码效率.FPGA验证结果表明,运用该结构的Tier-1编码器,在提高70%编码效率的同时只增加了18.2%的硬件开销,取得了令人满意的结果.

To satisfy the need of hardware implementation for JPEG 2000 encoder ,a high-performance architecture is proposed for the Tier-1 encoder that is the most complicated and time-consuming . The proposed architecture introduces pass-parallel bit-plane encoder which is based on stripe-skip algorithm within every pass to raise the coding speed .Meanwhile to work with the bit-plane encoder ,the MQ encoder utilizes a dynamic 5-stage pipeline to increase the coding efficiency more .The results of verification realized on FPGA show that the efficiency of Tier-1 encoder is raised 70% with the proposed architecture and it causes 18 .2% cost in hardware .Finally ,the results are acceptable .