期刊文献+

一种降低末级高速缓存污染的分阶段自适应动态插入策略

A Phase-Based Adaptive Dynamic Insertion Policy for Reducing Last Level Cache Pollution
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摘要 对多种末级高速缓存插入策略进行分析,并在动态插入策略DIP的基础上提出一种分阶段自我调整的动态插入策略,用于消除局部性差数据访问末级高速缓存造成的不良影响。实验结果表明,与现有LRU替换算法相比,此方法将末级高速缓存的MPKI平均降低了7.07%,即使与动态插入策略DIP相比,此方法也获得进一步的性能提升,末级高速缓存MPKI平均降低了4.36%。 The authors analyze multiple last level cache insertion policies and propose a phase-based adaptive dynamic insertion policy based on DIP (dynamic insertion policy) for eliminating the harmful effect of non-reusable data. The experiment result shows that in comparison with LRU (least recently used), the proposed approach can reduce the last level cache misses per thousand instructions, MPKI, 7.07% on average; even in comparison with DIP policy, the new approach can also improve last level cache performance in further, and average MPKI is reduced by 4.36%.
出处 《北京大学学报(自然科学版)》 EI CAS CSCD 北大核心 2014年第2期207-213,共7页 Acta Scientiarum Naturalium Universitatis Pekinensis
基金 国家科技重大专项(2009ZX01029-001-002) 863计划(2006AA010202)资助
关键词 末级高速缓存污染 软硬件协作 插入策略 last level cache pollution software and hardware collaboration insertion policy
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参考文献17

  • 1Hennessy J L, Patterson D. Computer architecture: a quantitative approach. 5th ed. San Francisco: Morgan Kaufmann, 2012.
  • 2Wm A W, Sally A M. Hitting the memory wall: implications of the obvious. ACM SIGARCH Computer Architecture News, 1995, 23:20-24.
  • 3Moinuddin K Q, Aamer J, Yale N P, et al. Adaptive insertion policies for high performance caching // Proceedings of the 34th annual international sym- posium on Computer architecture. San Diego: ACM, 2007:381-391.
  • 4Livio S, David T, Michael S. Redueing the harmful effects of last-level cache polluters with an OS-level,software-only pollute buffer//Proceedings of the 41 st annual IEEE/ACM International Symposium on Microarchitecture. Como, Italy: IEEE Computer Society, 2008:258-269.
  • 5David K T, Reza A, Livio B S, et al. RapidMRC: approximating L2 miss rate curves on commodity systems for online optimizations // Proceeding of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems. Washington: ACM, 2009:121-132.
  • 6Lu Q D, Lin J, Ding X N, et al. Soft-OLP: improving hardware cache performance through software- controlled object-level partitioning // Proceedings of the 2009 18th International Conference on Parallel Architeetures and Compilation Techniques. Raleigh, NC: IEEE Computer Society, 2009:246-257.
  • 7Kessler R E, Mark D H. Page placement algorithms for large real-indexed caches. ACM Transactions on Computer Systems, 1992, 10:338-359.
  • 8Lin J, Lu Q D, Ding X N, et al. Enabling software management for multicore caches with a lightweight hardware support//Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis. Portland: ACM, 2009.
  • 9Lin J, Lu Q D, Ding X N, et al. Enabling software management for multicore caches with a lightweight hardware support//Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis. Portland: ACM, 2009 Mazen K, Yan S. Counter-based cache replacement and bypassing algorithms. IEEE Computer Society, 2008, 57(4): 433-447.
  • 10Haakon D, Per S, Lasse N. An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches // Proceedings of the 2006 Workshop on Memory Performance: Dealingwith Applications, systems and architectures. Seattle: ACM, 2006:45-52.

二级参考文献10

  • 1邓让钰,陈海燕,邢座程,谢伦国,曾献君.EPIC微体系结构的存储级并行执行模型的研究[J].计算机学报,2007,30(1):74-80. 被引量:1
  • 2Christoforos Kozyrakis David Patterson. Scalable vector processors for embedded systems[J]. IEEE Micro, 2003,23 (6) : 36 - 45.
  • 3Junhee Lee, Chanik Park, Soonhoi Ha. Memory access pattern analysis and stream cache design for multimedia applications [ A ]. Asia and South Pacific Design Automation Conference [C]. New York:ACM,2003.22 - 27.
  • 4Jose R. Bnmheroto etc. Data cache prefetching design space exploration for BlueGene/L supercomputer[ A ]. SBAC-PAD' 05 E C ]. Washington , DC: lEvEE Computer Society?, 2005. 201 - 208.
  • 5J Weinberg,M o Mcracken, A Snavely, E Strohmaierm. Quantifying locality in the memory access patterns of HPC applications[ A]. SC2005 [ C ]. Washington, DC: IEEE Computer Society, 2005.50.
  • 6John McCalpin, Chuck Moore, Phil Hester. The role of multicore processors in the evolution of general-purpose computing [J]. CTWatch, 2007,3( 1): 18 - 30.
  • 7DAVE Turek. High performance computing and the implications of multi-core architecture[ J]. CTWatch, 2007,3(1) :31 - 33.
  • 8Jack Dongarra, Dennis Gannon, Geoffrey Fox, Ken Kennedy. The impact of multi-core on computational science software[J].CTWatch,2007,3(1) :3 - 10.
  • 9James Irwin, Simon Mclntosh-Smith. The best of both world: delivering aggregated performance for high-performance math libraries[Z]. ISC2007.
  • 10Yan Xuejun, Yan Xiaobo, Xing Zuocheng, Deng Yu, Jiang Jiang and Zhang Ying.A 64-bit stream processor architecture for scientific applications [A ]. ISCA2007 [ C ]. New York: ACM,2007. 210 - 21.

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