采用钳位二极管的新型低功耗SRAM的设计

Design of a new low power SRAM with clamping diode

给出了一种设计低功耗静态随机存储器(SRAM)的技术,实现了在电路级与架构级层次上同时降低漏电流与动态功耗。该技术采用源极偏压结构控制漏电流,将一个钳位二极管与NMOS管并联插入GND与SRAM单元的源极之间,当NMOS打开时SRAM进行正常的读写操作,而NMOS关闭则会将源极电压抬高至钳位电压,降低漏电流的同时保证了数据的稳定性;对SRAM结构进行独特的布局,引入Z译码电路,极大地减少每次操作时激活的存储单元数量,明显降低动态功耗;将power-gating技术与高阈值(highV_(th))器件相结合的低功耗设计应用于外围电路,进一步降低漏电流。基于UMC 55nm SP CMOS工艺制造了包含多个SRAM实例(instance)的测试芯片,测试结果证明了该技术的有效性与可靠性。

A new technique for design of a low power static random access memory （SRAM） was proposed to realize the simultaneous reduction of the leakage current and the dynamic power-consumption in the levels of circuit and archi- tecture. The technique adopts a source biasing scheme （ a NMOS transistor is inserted between the ground line and the SRAM cell）to reduce the leakage current. It requires an extra clamping diode in parallel with the NMOS tran- sistor to avoid the floating virtual ground voltage and obtain the data retention capability. The SRAM is in an active mode when the NMOS transistor is turned on. Turning off the NMOS transistor can raise the source voltage and lead to a large reduction in the leakage current. Besides, the memory architecture is uniquely partitioned to decrease the number of half-selected SRAM cells and thus reducing the dynamic power. Power-gating techniques combined with high-Vth devices are applied to low power periphery circuits. Test chips with kinds of embedded SRAM instances were fabricated in the UMC 55nm SP CMOS process and the measurement results proved the effectiveness and relia- bility of the proposed technique.