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基于SOI工艺集成电路ESD保护网络分析与设计

Analyze and Design of ESD Protection Network for Integrated Circuit on SOI Process
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摘要 由于SOI(Silicon-On-Insulator)工艺采用氧化物进行全介质隔离,而氧化物是热的不良导体,因此SOI ESD器件的散热问题使得SOI电路的ESD保护与设计遇到了新的挑战。阐述了一款基于部分耗尽SOI(PD SOI)工艺的数字信号处理电路(DSP)的ESD设计理念和方法,并且通过ESD测试、TLP分析等方法对其ESD保护网络进行分析,找出ESD网络设计的薄弱环节。通过对ESD器件与保护网络的设计优化,并经流片及实验验证,较大幅度地提高了电路的ESD保护性能。 Oxide is used for Full-Isolation on SOI technology, but its low thermal conductivity reduces the protection level offered for Electrostatic Discharge(ESD). The protection design of SOI Integrated Circuit is up against a new challenge. In the paper, build up a ESD protection network for a Digital Signal Processing (DSP)on partial deplete(PD)SOI process, ifnd out the weakness of the network by ESD Test/TLP and correct it. As a result, the ESD protection level of the circuit was upgraded obviously.
出处 《电子与封装》 2014年第3期29-32,40,共5页 Electronics & Packaging
关键词 集成电路 ESD保护设计 可靠性 SOI integrated circuit SOI design of ESD protection reliability
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参考文献3

  • 1Mansun Chan, Selina S Yuen, ZhiJian Ma, et al. Comparison of ESD Protection Capability of SO1 and BULK CMOS output Buffers [J]. IEEE/IRPS, 1994: 292-298.
  • 2S Voldman, R Schulz, J Howard, et al. CMOS-on-SOI ESD Protection networks [J]. EOS/ESD Syrup, 1998: 333-350.
  • 3罗静,颜燕,罗晟,洪根深,胡永强.抗辐照SOI 256kB只读存储器的ESD设计[J].电子与封装,2011,11(9):27-31. 被引量:1

二级参考文献4

  • 1Ming-Dou Ker, Kei-Kang Huang, Tien-Hao Tang. Silicon-on-insulator diodes and ESD protection circuits: United States, US 6653670B28[P]. Nov.25,2003.
  • 2Mansun Chan, Selina S Yuen, Zhi-Jian Ma, et al Comparison of ESD Protection Capability of SOI and BULK CMOS output Buffers[J]. IEEE/IRPS, 1994:292-298.
  • 3Sridhar Ramaswarmy, Prasum Raja, et al. EOS/ESD Protection Circuit Design for Deep Submicron SOI Technology[J]. EOS/ESD Symp, 1995:212-217.
  • 4S Voldman, R Schulz, J Howard, et al. CMOS-on-SOI ESD protection networks[J]. EOS/ESD Symp,1998:333-350.

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