可扩展和低功耗FPGA全定制配置电路设计

Scalable and Low-power FPGA Programming/Downloading Full Custom Circuit Design

针对现场可编程逻辑阵列(FPGA)器件规模日益扩大带来的FPGA编程下载电路扩展性和功耗问题,采用层次化和模块化方法设计编程下载全定制电路,引入新的器件"左""右"分区选择信号,去耦合列地址和帧地址,同时用硬件可编程思想设计字线/位线基本控制单元.实验结果表明该设计有效解决了FPGA编程下载全定制电路部分的扩展性问题,适用于同系列不同规模的FPGA设计,并且与常规设计相比,全定制配置电路即字线和位线控制电路在面积分别仅增加0.6%和0.1%的代价下,功耗分别降低了46.6%和49.6%.

As FPGA＇s is becoming larger, the scablilty, reusability, power consumption issue of the programming/ downloading circuit gets more complex. A hierarchy and modular custom circuit of programming/downloading is proposed： new hierarchy addresses LeftE/RigtE are used, column address and frame address are decoupled, wordline^bitline controllers are designed to be reusable. The design makes the programming/downloading circuit easy to expand and reuse with reducing power consumption of wordline controller by 46.6% and bitline controller by 49. 6 %, at the cost of increasing WL controller and BL controller circuits area by only 0. 6 ~ and 0.1%.