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绝缘体上全局应变硅晶圆的制备和表征

Fabrication and Characterization of Global Strained Si on Insulator
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摘要 首先使用改良型Ge浓缩法制备了绝缘体上锗硅圆片,然后在超薄弛豫SiGe层上,利用超高真空化学气相沉积法外延了单晶硅薄膜,获得一系列不同厚度的6寸绝缘体上应变硅晶圆。结果表明应变硅薄膜完整、均匀、表面平整且晶体质量良好,获得样品中顶层硅最大应力值达2.22 GPa。应用临界厚度理论对样品厚度和应变值之间的关系进行了分析,发现本实验所得样品在超过临界厚度3倍之后会发生应变弛豫。 Firstly, SiGe on insulator (SGOI) wafers were fabricated by modified Ge condensation technology, then single crystal Si films were epitaxially deposited on the ultra-thin relaxed SiGe layer by ultra-high vacuum chemical vapor deposition (UHVCVD). Finally, a series of strained Si wafers with different thickness were obtained. The results indicate that the strained Si layers were complete and uniform, with a flat surface and high quality crystal lattice. The highest stress attained 2.22 GPa. The relation between strain and thickness was analyzed using theory of critical thickness, and it was found that the strained Si samples in this paper did not relax until the thickness reached triple critical one.
出处 《人工晶体学报》 EI CAS CSCD 北大核心 2014年第2期420-425,共6页 Journal of Synthetic Crystals
基金 国家自然科学基金(61306007) 河南省教育厅科学技术研究重点项目(14A510004) 南阳师范学院专项项目(ZX2012017)
关键词 应变硅 硅薄膜 锗浓缩 临界厚度 strained Si Si film Ge condensation critical thickness
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  • 1Bhushan S, Sarangi S, Santra A, et al. An Analytical Surface Potential Model for Strained-Si on Siilicon-Germanium MOSFET Including the Effects of Interface Charges[ J]. Journal of Electron Devices ,2012,15 : 1285-1290.
  • 2Thompson S E, Guangyu S, Youn Sung C, et al. Uniaxial-process-induced Strained-Si: Extending the CMOS Roadmap [ J ]. Electron Devices, IEEE Transactions ,2006,53 (5) : 1010-1020.
  • 3Morin P, Ortolland C, Mastromatteo E, et al. Mechanisms of Stress Generation within a Polysilicon Gate for n-MOSFET Performance Enhancement [ J ]. Materials Science and Engineering B-Solid State Materials for Advanced Technology, 2006,135 ( 3 ) : 215-219.
  • 4Pradhan K P, Mohapatra S K, Sahu P K. An Analytical Surface Potential and Threshold Voltage Model of Fully Depleted Strained-SOl MOSFETs in Nanoscale With High-k Gate Oxide[ C ]. Emerging Technology Trends in Electronics, Communication and Networking (ET2ECN), 2012 1 st International COnference on 2012. Surat, Gujarat, India : IEEE.
  • 5Ghyselen B, Hartmann J M, Ernst T, et al. Engineering Strained Silicon on Insulator Wafers with the Smart CutTM Technology [ J ]. Solid-state Electronics, 2004,48 ( 8 ) : 1285-1296.
  • 6Allibert F, Cheng K, Vinet M, et al. Evaluation of sSOI Wafers for 22 nm Node and Beyond[ C]. SOI Conference (SOI), 2012 IEEE International. 2012. NAPA, CA: IEEE.
  • 7Mungufa J, Bluet J-M, Marty O, et al. Temperature Dependence of The Indirect Bandgap in Uhrathin Strained Silicon on Insulator Layer[ J ]. Applied Physics Letters, 2012,100 ( 10 ) : 102107-4.
  • 8Ma X B, Liu W L, Liu X Y, et al. Strain Stability and Carrier Mobility Enhancement in Strained Si on Relaxed SiGe-on-Insulator[ J ]. Journal of the Electrochemical Society,2010,157( 1 ) :104-108.
  • 9戴显英,王琳,杨程,郑若川,张鹤鸣,郝跃.机械致单轴应变SOI晶圆的制备[J].西安电子科技大学学报,2012,39(3):209-212. 被引量:2
  • 10Liu X Y, Ma X B, Du X F, et al. Modified Postannealing of the Ge Condensation Process for Better-Strained Si Material and Devices[J]. Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures ,2010,28 (5) :1020-1025.

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