高速路由器中并行化调度器的体系结构

Architecture of a parallel flow scheduler for the traffic manager in a high speed router

目前路由器不仅要满足传输带宽的需求,还需要保证用户服务质量。业务量管理器是路由器中的一个重要芯片,负责调度网络流,为用户提供服务质量保证。单个业务量管理器所能支持的带宽受限于硬件的工作频率、数据总线、设计工艺等,难以满足高速率接口,如100Gb/s以太网的要求。又由于路由器内部的空间非常拥挤,如果在路由器的一块线卡上部署多个业务量管理器芯片以满足高带宽的需求,将使得线路板体积增大,成本和功耗也相应增大。为提高单个业务量管理器芯片的处理能力,该文设计了一种支持多线程处理的并行化调度器。并行化调度器采用二级调度策略,能够在不提高系统内部时钟频率的基础上,成倍提高业务量管理器的调度速度;而且并行化调度器共享片外存储器,可以充分利用存储器带宽,减少存储器数目。性能评价结果表明:利用支持4线程的并行化调度器实现的业务量管理器的最大支持带宽可提高3倍;相比于部署4个业务量管理器芯片的方案,4线程方案的片内存储开销、逻辑开销和存储器使用数量分别降低了7.1%、36.2%和75%,而且4线程方案的部署空间和存储器功耗开销都降低了75%。

Current routers not only need to guarantee the bandwidth requirement, but also need to guarantee the quality of service （QoS）. As one of the most important chips in the router, the traffic manager is responsible for scheduling the input packets and guaranteeing the QoS. The traffic manager throughput is limited by the system frequency, the data bus and the design, so one traffic manager can not meet all the requirements of a high speed network interface （for example, a 100 Gb/s interface）. Routers all alreadycrowded and multiple traffic manager chips to increase the throughput will increase the size of the line card, the cost and the power consumption. This paper describes a high speed traffic manager that uses a parallel scheduler architecture with two stage scheduling and multi-threading. This traffic manager increases the throughput without increasing the system clock frequency. The parallel scheduler shares one ofgchip memory which reduces the number of off-chip memory chips and improves the bandwidth utilization. Evaluations show that the throughput of a 4-thread parallel traffic manager with the parallel scheduler is increased 3 fold. Compared with 4 traffic managers, this system reduces the on-chip memory cost by 7.1%, the logic element cost by 36.2%and the number of off-chip memory chips by 75%. The space cost and the power consumption of the off-chip memories are both reduced by 75%o.