低噪声、低功耗微电容读出ASIC设计

Design of Low Noise and Low Power Microcapacitance Readout ASIC

针对差分电容式微电子机械系统(MEMS)加速度计,设计了一种低噪声、低功耗微电容读出专用集成电路(ASIC)。电路采用开关电容结构,使用相关双采样(CDS)技术降低电容-电压(C-V)转化电路的低频噪声和偏移电压。通过优化MEMS表头噪声匹配、互补金属氧化物半导体(CMOS)开关和低噪声运算放大器来降低频带内的混叠热噪声。采用电源开关模块和门控时钟技术来降低电路功耗,同时集成自检测电路和温度传感器。采用混合CMOS工艺进行流片加工,测试结果表明,优化后ASIC的电容分辨率为槡1.203 aF/Hz,系统分辨率为0.168 mg(量程2 g),芯片功耗约为2 mW。同时,该ASIC还具有很好的上电特性和稳定性。

A low noise and low power microcapacitance readout application specific integrated cir- cuit （ASIC） was designed for the differential capacitance micro-electromechanical systems （MEMS） accelerometer. Switch-capacitor structure was selected in this circuit, and correlated double sampling （CDS） technology was used to reduce the C-V sub-circuit low frequency noise and offset voltage. The in- band aliased noise was reduced by optimizing the MEMS fronted capacitance noise matching, comple- mentary metal oxide semiconductors （CMOS） switch and low-noise amplifier. Switch power module and gated clock technology were selected to decrease the circuit power. Meanwhile, the circuit included self- test circuit and temperature sensor. This circuit was manufactured using mixed CMOS technology. The test results show that the optimized capacitor resolution of ASIC is 1. 203 aF/√Hz, the resolution of the system is 0. 168 mg （range is 2 g） , and the total power is about 2 mW. Meanwhile, ASIC has better start-up and stability characteristic.