基于FPGA的点阵显示电子计时器设计

Design of the Dot Matrix Display Electronic Timer Based FPGA

本文介绍基于FPGA的点阵显示电子计时器的设计,该设计较多地综合数字逻辑电路知识,将门电路、变量译码器、数据选择器、计数器和只读存储器应用于工程,变量译码器作为数据分配器使用。把它作为可编程器件开发的教学实验课题具有实用性和趣味性,可进一步提高数字逻辑电路和可编程器件应用的实验教学水平。

This paper describes the design of the dot matrix display electronic timer based FPGA. There is plenty of comprehensive digital logic circuit knowledge involved in the project. It utilizes gate circuit, variable decoder, data selector, digital counter and ROM in engineering application. The Variable decoder serves as data distributor. It can be used as a teaching material to develop a programmable logic device due to its practical and interest nature. It will bring the teaching and experiment of digit logic circuit and programmable logic device to a new level.