锁相环的设计与性能分析

Design and Performance Analysis of Phase-locked Loop

锁相环诞生以来,已越来越广泛地应用于科研、生产、生活中。在现阶段应用最广泛的数字鉴相器加模拟环路滤波器的混合信号锁相环(数字锁相环)结构中,大量使用一阶有源环路滤波器来实现二阶锁相环系统,满足了绝大部分应用的需要。在介绍了锁相环基本原理及结构功能的基础之上,对锁相环的设计方法进行了探讨,利用Matlab进行了仿真验证,并对所设计的锁相环的性能指标进行了分析。

Since its emergence, the phase-locked loop（PLL） has been more and more widely used in scientific research, industry and life. The currently most popular digital phase-locked loop takes the structure of digital phasometer and analog loop filter, which massively uses the first-order active loop filter to achieve the second-order phase-locked loop system and meets the needs of the majority of applications. This paper firstly introduces the basic principles, structure and functions of the phase-locked loop, then explores the design methods, simulates and vivificates in MATLAB, and finally analyzes the performance of the phase-locked loop（PLL） designed.