时序敏感的容软错误电路选择性加固方案

Timing-aware selective hardening technique for soft-error-tolerance

由于瞬态故障引起的电路软错误问题越来越严重,现有的选择性加固方案通常带来较大的时序和面积开销。针对这些问题,提出了在电路时序松弛路径使用高可靠性时空冗余触发器来加固电路的方案。该方案在不降低电路性能且面积开销很小的情况下,达到电路容错性能的最大提高。ISCAS’89基准电路的实验数据显示,平均面积开销为60.26%就能将整个电路的软错误率降低90%以上。针对可靠性、性能和面积开销,提出了综合评价指标RAPP。本方案在加固30%、50%、70%和90%时,和相关文献相比,RAPP值都是最小的,达到了三者的最佳折中。

Because the digital circuit soft error problem caused by transient fault is getting worse,the existing circuit hardening techniques usually reduce the performance of circuit and serious area overhead are unacceptable.To solve the problem,high reliability temporal redundancy flip-flop is used to hardening circuit on the path of timing slack.This technique can achieve the maximum improvement of circuit fault-tolerant without reducing the performance of circuit,and the area overhead is small.The experimental data of ISCAS＇ 89 benchmark circuits show that it can reduce the soft error by more than 90％ at average area overhead of 60.26％.For reliability,performance and area overhead,a comprehensive evaluation metric RAPP is proposed.The proposed technique is the smallest of the three product at hardening of 30％,50％,70％ and 90％,compared with other relative techniques,reached better tradeoff between reliability,performance and area overhead.