3D NoC中柔性可配置的高可靠路由器设计

Design of flexible and configurable high-reliability router in 3D Network on-Chip

三维片上网络中路由器发生故障及拥塞等可靠性问题,会影响整个网络性能。因此针对路由器输入缓存的故障和拥塞问题,提出一种柔性(flexible)可配置的高可靠路由器架构。每条输入链路和2个相邻的输入缓存相连。通过建模,根据具体的故障和拥塞情况,选择合适的输入缓存路径,实现部分缓存的共享。不仅能达到路由器故障的容错目的,还能在网络重负载的情况下有效的解决网络拥塞问题。实验结果表明,方案相较于传统路由器方案,在一般传输模式和0.5 filts/node/cycle的注入率下,无故障时平均时延下降了81.89%,2个数据分配器故障时平均时延下降了87.38%。在网络出现故障和拥塞时,方案具有明显的优势,很好的保证了整个网络的高可靠性以及低时延。

The reliability problems such as faults and congestion occurring in router will greatly affect the performance of the entire network in 3D network on-chip.Aiming at the faults and congestion in input buffer,this paper proposes a flexible and configurable high-reliability router architecture,each input channel is connected to two adjacent buffers.By means of modeling,the router architecture selects appropriate input buffer path to achieve partial buffer sharing on the basis of the specific fault and congestion.This method can not only achieve the goal of faulttolerance for router fault,but also efficiently solve the congestion problem of the entire network under the heavy network load.The experiment results show that,compared to the conventional router architecture,the proposed scheme in this paper has 81.89％ less average network latency without faults and 87.38％ less average network latency in the presence of 2 DE multiplexer fault under uniform traffic pattern and 0.5flits/node/cycle.This scheme has obvious advantage and ensures the high-reliability and low-latency of the entire network when congestion and faults occur.