Design of systolic B^N circuits in Galois fields based on quaternary logic

The BN operation is known as an efficient basic operation in Galois fields GF （2k）, and various algorithms and implementations using binary logic signals have already been proposed. In or- der to reduce the circuit complexity and long latency of BN operations, a novel algorithm and its sys- tolic architecture are proposed based on multiple-value logic （MVL）. In the very large scale integra- tion （VLSI） realization, a kind of multiple-valued current-mode （MVCM） circuit structure is presen- ted and in which the combination of dynamic source-coupled logic （SCL） and different-pair circuits （DPCs） is employed to improve the switching speed and reduce the power dissipation. The perform- ance is evaluated by HSPICE simulation with 0.18 μm CMOS technology. The transistor numbers and the delay are superior to corresponding binary CMOS implementation. The combination of MVCM cir- cuits and relevant algorithms based on MVL seems to be potential solution for high performance a- rithmetic operationsin Galois fields GF（2k）.