2CLIFFORD E CUMMINGS.Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Dsigns[A].SNUG San Jose,CA Voted Best Paper 3rd Place[C],2001:2-4,16-23.
3周景润.OrCAD&PADS高速电路板设计与仿真[M].北京:电子工业出版社.2007.
4PO-KAI HUANG, CHENG-SHANG CHANG,JAYCHENG,DUAN-SHIN LEE.Recursive Constructions of Par- allel FIFO and LIFO Queues with Switched Delay Lines [J].IEEE Transactions on Information Theory,2007,5(5): 1778-1785.
5RYAN W.APPERSON,ZHIYI YU,MICHAEL J.MEEUWSEN, TINOOSH MOHSENIN,BECAN M.BAAS. A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains[J].IEEE Transac- tions on Very Large Scale Integration(VLSI) System,2007 (10): 1125-1131.
6SHOUQIAN YU,LILI YI,WEIHAI CHEN,ZHAOJIN WEN.Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA[C].2007 Second IEEE Conference on Industrial Electronics and Applications, 2007,2633-2638.
7XILINX INC.Virtex-4 FPGA USER GUIDE [Z/OL]. http.//www, xilinx, com. December 1,2008.
8FEI LI.Competitive FIFO Buffer Management forWeighted Packets[C].2009 Seventh Annual CommunicationNetworks and Services Research Conference,2009, 126-132.
9Dual Channel14-/12-Bit,250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs[Z].Texas Instruments,2009.
