期刊文献+

一种模数混合结构的延迟锁相环设计

Design of A Kind of Hybrid-structure Delay Locked Loop
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摘要 数字系统通信的不断发展,多种延迟锁相环结构的出现满足了不同应用要求。提出了一种模/数混合结构的延迟锁相环,改善了传统模拟锁相环和传统数字锁相环各自的缺点,在数字系统中作为集成电路模块单元使用。采用TSMC的0.25μm,1P5M,CMOS混合信号工艺进行加工制备,模块单元面积140×190μm2。 With the development of digital communication system, the advent of several structures of delay locked loop can satisty the demand of specs in different applications. An analog - digital hybrid - structural delay locked loop,as an IC - modular utilized in a large scale digital system, which improved the drawbacks of traditional analog DLL and digital DLI,', is described in this paper. TSMC 0.25μm, 1PSM,CMOS mixed -signal process are used in the circuit with the modular area of 140 ×190μm2.
出处 《微处理机》 2014年第2期11-12,共2页 Microprocessors
关键词 延迟锁相环 混合结构 集成电路模块 Delay locked loop (, DLL) Hybrid - structure IC - modular
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参考文献3

  • 1YMoon, et al. An all -analog multiphase delay -locked loop using a replica delay line tbr wide - range operation and low - jitter peflbrmance [ J ]. IEEE J. Solid - State Circuit ,2000,35 ( 3 ) :377 - 384.
  • 2Y Okajima, M Taguchi. Digital delay locked loop an design technique tor high - speed synchronous interface [J].IEICE Trans. Electnm,1996,E79-C(6):798- 807.
  • 3HH Chang, S J l,iu. A wide - range and t~.st - locking ~dl - digital cycle - controled DLL [ J ]. IEEE J. Solid - State Circuit ,2005,40( 3 ) :661 - 670.

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