3D SoC的多频测试架构设计

Multi-frequency test architecture design on 3D SoC

随着芯片集成度的提高,三维片上系统(three-dimensional System on Chip,3DSoC)是集成电路发展的必然趋势,其中可测性设计成为研究的重点.为了降低测试代价,提出一种符合工业实际的多频测试架构及适用于该架构的测试算法,并结合功耗对测试架构进行了仿真实验.实验结果表明,与传统的SoC相比,在同样TAM测试数据位宽数限制下,多频架构的3DSoC测试时间更短,测试代价更小.

With the improvement of circuit integration, 3D SoC （three-dimensional System on Chip） is a new trend of SoC （System on Chip）, and the design for testability of 3D SoC becomes the focus. To re- duce the test cost, a new multi-frequency test architecture is designed and the corresponding algorithm combined with the power consumption is proposed,which is tested on the platform. The experiment re- suits show that the testing time and cost can be less than the traditional SoC with the same test data width of TAM.