基于附加信号回波抵消的FPGA实现

FPGA Implementation of Echo Cancellation Based on Additional Signal

针对基于附加信号回波抵消在硬件设计中出现的迭代误差累积导致信道估计不准确和耗费大量FPGA资源的问题,对算法进行了改进。从主径开始估计回波信道的方法,提高了信道估计精度和减少了FPGA资源消耗。然后,在FPGA平台上用硬件语言Verilog HDL对此回波抵消系统加以实现。仿真结果表明此设计在回波抵消方面具有良好的效果。

For the problem that iteration error accumulation which leads to channel estimation inaccurate and consumes a lot of FPGA resources occurs in the hardware design of echo cancellation based on additional signal, it improved the algorithm. The method of estimating echo channel from the main path has improved the accuracy of channel estimation and reduced the FPGA resource con- sumption. Then it achieved the echo cancellation system using Verilog HDL language on FPGA. Simulation results show that the de- sign has better effect of echo cancellation.