期刊文献+

结构测试生成中被测电路描述文件转换方法研究

Study on Transfer Method of Circuit Description File in Structure Testing Generation
下载PDF
导出
摘要 自动测试向量生成技术是对数字集成电路的结构进行测试并能对故障进行定位的先进测试方法.针对普通研究人员无法有效利用现有测试生成软件的问题,提出了基于Windows操作系统的数字集成电路测试生成平台.为了使计算机能够识别被测电路的结构并自动生成测试向量,重点研究了将常用的bench格式描述文件转换为lev格式网表文件的方法,分析了文件转化算法以及相关的电路级数和可测性算法,给出了实现这些算法的软件流程.最后,利用所提出的算法成功地对C17,C432等11个组合基准电路文件进行了转换,并且将形成的lev文件应用于自动测试向量生成中,证明了程序的正确性. The automatic test pattern generation (ATPG)technology is an advanced testing method by which the faults can be located through testing the structure of digital integrated circuit. Aiming at the problem that ordinary researchers cannot use effectively the existing test generation software, a test generation platform of digital integrated circuit based on Windows operating system is put forward. In order to identify the structure of the tested circuit by computer and generate test vectors automatical- ly, a method to convert the common description file of bench format into the netlist file of lev format is studied emphatically. The algorithms of file transfer, circuit progression and measurability are analyzed, and the software workflows to realize these algorithms are provided. Finally, C17, C432 and other 11 combinational benchmark circuits files are successfully transferred based on algorithms, then the generated lev format files are applied to ATPG. The results prove that the transfer program is correct.
作者 王康谊
出处 《中北大学学报(自然科学版)》 CAS 北大核心 2014年第2期191-197,共7页 Journal of North University of China(Natural Science Edition)
基金 山西省留学基金资助项目(2011-072)
关键词 数字集成电路 结构测试 bench文件 lev文件 digital integrated circuit structure testing bench file lev file
  • 相关文献

参考文献7

二级参考文献63

  • 1BOUWMAN F, OOSTDIJK S, STANS R, et al. Macro testability: the results of production device applications[ A ]. Proc International Test Conference [ C ].[s.l.] :[s.n. ], 1992.
  • 2MARINISSEN E J, KUIPER K, WOUTERS C. Testability and test protocol expansion in hierarchical macro testing [ A ]. Proceedings of ETC 93 [ C].[s.l. ] :[s. n. ] ,1993.
  • 3MARINISSEN E J, LOUSBERG M. The role of test protocols in testing embedded - core - based system ICs[A]. Proc European Test Workshop [C].[s. l. ] :[s. n. ] ,1999.
  • 4HUANG Xiaolu, ZHANG D, MIN Y. Module - based hierarchical test generation for combinational circuits at register - transfer level [A ]. IEEE WRTLT' 01 [ C].[s. l.] :[s.n. ] ,2001.
  • 5MARKRIS Y, COLLINS J. Transparency - based hierarchical test generation for modular RTL designs [ A].IEEE International Symposium on Circuits and System[C]. [s.l. ]:[s. n. ], 2000.
  • 6YAKRIS Y, ORAILOGLU A. DFT guidance throug hRTL test justification and propagation analysis [ A ].Proc International Test Conference[C].[s.l. ] :[s.n. ], 1998.
  • 7MARKRIS Y, ORAILOGLU A. Channel- based behavioral test synthesis for improved module reachability[ A ]. Proc Europe Conference and Exhibition, Design,Automation and Test[ C]. [ s.l. ]: [ s. n. ], 1999.
  • 8BHATIA S, JHA N K. Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits [ J ]. IEEE Transactions on VeryLarge Scale Integration (VLSI) Systems, 1998, 6(4):608 -619.
  • 9GHOSH I, RAGHU A, NATHAN N,JHA K. Hierarchical test generation and design for testability methods for ASPPs and ASIPs[J]. IEEE Trans On Computer-Aided Design of Integrated Circuits and Systems, 1999,18(3):357 -370.
  • 10GHOSH I, FUJITA M. Automatic test pattern generation for functional register - transfer level circuits using assignment decision diagrams [ J ]. IEEE Transactionson Computer - Aided Design of Integrated Circuits and Systems, 2001, 20(3) : 402-415.

共引文献9

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部