基于IBIS模型的高速数字I/O缓冲器的瞬态行为建模

Transient Behavioral Modeling of High-Speed Digital I/O Buffer Based on IBIS Model

引入了一种基于最新版本的 IBIS模型给出的信息构造高速数字 I/O缓冲器的瞬态行为模型的方法 .阐述了从 IBIS建模数据中得到这种瞬时状态转换行为模型的推导过程 ,同时获得了建模所需要的充分条件 .与相应的晶体管级模型相比 ,该方法在获得了更高仿真精度的同时 ,提高了具有大量同步开关器件芯片互连的仿真速度 .最后 ,为了验证模型的有效性 ,给出了该模型和晶体管级模型 (SPICE模型 )

An approach for building a transient behavioral model of high speed digital I/O buffers based on the information of the latest version IBIS model was introduced. The derivation procedures of such transient state transition behavioral models from IBIS modeling data was mainly dealt with, and the sufficient condition for modeling was obtained. This scheme speeds up the simulations of chip interconnect with a large number of simultaneous switching devices, while acquiring better accuracy compared to the corresponding transistor level models. A comparison of simulation results between these models and transistor models (SPICE models) was made to verify the efficiency.