摘要
A novel approach to survivor memory unit of Decision Feedback Sequence Estimator(DFSE) for 1000BASE-T transceiver based on hybrid architecture of the classical register-exchange and trace-back methods is proposed.The proposed architecture is investigated with special emphasis on low power and small decoder latency,in which a dedicated register-exchange module is designed to provide tentative survivor symbols with zero latency,and a high-speed trace back logic is presented to meet the tight latency budget specified for 1000BASE-T transceiver.Furthermore,clock-gating register banks are constructed for power saving.VLSI implementation reveals that,the proposed architecture provides about 40% savings in power consumption compared to the traditional register-exchange architecture.
A novel approach to survivor memory unit of Decision Feedback Sequence Estimator （DFSE） for 1000BASE-T transceiver based on hybrid architecture of the classical register-exchange and trace-back methods is proposed. The proposed architecture is investigated with special emphasis on low power and small decoder latency, in which a dedicated register-exchange module is designed to provide tentative survivor syml^ols with zero latency, and a high-speed trace back logic is presented to meet tile tight latency budget specified for 1000BASE-T transceiver. Furthermore, clock-gating register banks are constructed for power saving. VLSI implementation reveals that, the proposed architecture provides about 40% savings in power consumption compared to the traditional register-exchange architecture.
