低噪声整数频率合成芯片的设计

Design of Low Noise Integer-N Frequency Synthesizer Chip

设计了一个锁相环频率合成芯片。该芯片集晶体振荡电路、鉴频鉴相器、电荷泵、分频器、低通环路滤波器和压控振荡器（VCO）等电路于一体。详细分析了频率综合器中的各个关键模块，利用MATLAB软件优化环路参数，简化了电荷泵、VCO和片内环路参数的相关设计。最后，给出了芯片照片和流片测试结果，验证了设计方法和电路设计的正确性。该芯片在0．35p．mCMOS工艺下进行了流片，测试结果表明，电源电压3V，电流25mA，芯片面积为5．4mm。（3000μm×1800μm）。输出频率0．8～1．2GHz，步进50MHz，单边带相位噪声优于-106dBc／Hz@1kHz，-106dBc／Hz@10kHZ，-115dBc／Hz@100kHZ，-124dBc／Hz@1MHz，-140dBc／Hz@10MHz．

A phase-locked loop （PLL） frequency synthesizer chip was designed. The chip consists of crystal oscillator, frequency phase detector, charge pump, frequency divider, low-pass filter and voltage controlled oscillator （VCO） , etc. Each key modules in frequency synthesizers were analyzed in detail. The MATLAB software was used to optimize loop parameters and significantly simplified the cor- relative design of charge pump circuit, VCO and loop parameters in the chip. Finally, the photographs of the chip and test results were presented, which demonstrated the design method and the circuits de- sign. The chip was fabricated in a 0. 35 μm CMOS process. The test results show that the area of the chip is 5.4 mm2 （3 000 μm×l 800 μm） and the work current is 25 mA with a 3 V supply. The output frequency ranges from 0. 8 to 1.2 GHz and the frequency step is 50 MHz. The single band phase noise at 1 kHz offset is below -106 dBc/Hz, at 10 kHz offset is below -106 dBe/Hz, at 100 kHz offset is below -115 dBc/Hz, at 1 MHz offset is below -124 dBc/Hz, at 10 MHz offset is below -140 dBc/Hz.