高速低功耗自适应可编程分频器

A Self-Adaptive Configurable High-Speed Low-Power Frequency Divider

在约翰逊计数分频器的基础上,设计了一款双级结构分频器,采用系数自适应分配技术,显著提升了分频器的工作频率,并有效降低功耗。基于45nm CMOS工艺进行仿真,结果表明:该分频器最高工作频率可达8GHz,在1GHz时,49分频的双级可编程分频器功耗仅为63μW,在8GHz时,功耗为312μW。与典型的约翰逊结构相比,双级分频器工作频率可提升1.6倍,在分频器系数设置为6时,最大功耗优化比达到51.82%。

Based on conventional structure of Johnson counter consisting of D-type flip-flops,a novel two-stage divider was proposed.In this circuit,operating frequency was significantly improved and power consumption was effectively reduced by using factor adaptive distribution technique.Results from simulation based on 45nm CMOS process showed that the frequency divider had a maximum operating frequency up to 8 GHz,and the ÷49 programmable two-stage divider consumed a power of only 63μW and 312μW,when operating at 1GHz and 8 GHz,respectively.The operating frequency of the proposed two-stage divider was improved by about 1.6times, and the power optimized ratio was 51.82% for a dividing factor of 6,compared with typical Johnson counter frequency divider,.