期刊文献+

快闪存储器阈值电压分布读取和修正方法

Threshold Voltage Reading and Correcting Method for Flash Memory
下载PDF
导出
摘要 在快闪存储器中,多晶硅浮栅的漏电、存储单元之间的干扰、长期的编程擦除操作都会使存储单元的阈值电压发生漂移,使采用多电平技术的快闪存储器的阈值电压分布规划变得越来越困难。针对这一问题,提出了一种快闪存储器阈值电压分布读取方法,该方法能准确地测量快闪存储器的阈值电压分布,给快闪存储器阈值电压分布规划和编程擦除算法的设计提供参考。 In flash memory, the leakage from the floating gate, crosstalk among memory cells and long erase/program operation will make the memory cell's threshold voltage drift. As a result, planning threshold voltage distribution for multi-level cell is becoming more and more difficult. To solve this problem, a reading and correcting method for flash memory threshold voltage distribution is presented in this paper. This method can accurately measure threshold voltage distribution of flash memory, which is valuable for the plan of programming and erasing algo- rithm in multi-level cell.
出处 《固体电子学研究与进展》 CAS CSCD 北大核心 2014年第2期174-178,共5页 Research & Progress of SSE
基金 国家自然科学基金资助项目(61106102)
关键词 快闪存储器 阈值电压分布 多电平 Flash memory threshold voltage distribution multi-level cell
  • 相关文献

参考文献8

  • 1Yuu Maeda, Haruhiko Kaneko. Error control coding for multilevel cell flash memories using nonbinary low- density parity-check codes [C]. IEEE in ternational Symposium on Defect and Fault Tolerance in VLSI Systems, 2009 : 367-375.
  • 2Boaz Eitan, Paolo Pavan, Ilan Bloom, et al. NROM.. A novel localized trapping, 2 bit nonvolatile memory cell[J]. IEEE Electron Device Letters, 2000,21 (11): 543-545.
  • 3Daeyeal Lee, Ik Joon Chang, SangYong Yoon, et al. A 64 Gb 533 Mb/s DDR interface MLC NAND flash in Sub-20 nm technology[C]. IEEE international Solid- state Circuits Conference, 2012 : 430-432.
  • 4Marotta G, Macerolal A, D'Alessandro A, et al. A 3 bit/Cell 32 Gb NAND flash memory at 34 nm with 6 MB/s program throughput and with dynamic 2 b/Cell blocks configuration mode for a program throughput increase up to 13 MB/s[C]. IEEE international Solid- state Circuits Conference, 2010 : 444-446.
  • 5Bauer M, Alexis R, Atwood G, et al. A multilevel cell 32 Mb flash memory[C]. IEEE international Solid-state Circuits Conference, 1995: 132-133.
  • 6Hiroshi Iwai, Hisayo Sasaki Momose. Ultrathin gate oxides-performance and reliability[C]. Proceedings of in ternational Electron Devices Meeting ( IEDM), IEEE, 1998:163-166.
  • 7Nair D R, Mohapatra N R, Mahapatra S, et al. Effect of P/E cycling on drain disturb in flash EEPROMs un- der CHE and CHISEL operation[J]. IEEE Transactions on Device and Materials Reliability, 2004, 4 (1) : 3237.
  • 8Prall K. Scaling Non-volatile memory below 30 nm [C]. Proceedings of Non-volatile Semiconductor Memory Workshop(NVSMW), IEEE, 2007 :26-30.

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部