非规则LDPC码编码器的FPGA实现

Implementation of Irregular LDPC Code Encoder FPGA

文中硬件实现了一种非规则的低密度奇偶校验码在一定的约束条件下,利用具有一定结构的校验矩阵来降低编码复杂度的LDPC码,并给出了编码器设计实现原理、结构和基本组成。在Quartus 9.0软件平台上采用基于FPGA的Verilog硬件描述语言,在Altera的Cyclone系列型号为EP1C6Q240C8N的芯片硬件平台实现了整个编码过程中所有模块的功能,并通过Matlab验证了编码结果的正确性。同时,该编码方案还可灵活应用于不同码长的系统中。

This article implements the rules of a kind of low density parity check code （LDPC） on hardware. Under the condition of certain constraints, a check matrix structure is used to reduce the encoding complexity of LD- PC codes. The design principle, structure and basic composition of the encoder are given. All module functions in the entire coding process are achieved using FPGA Verilog hardware description language on the Quartus 9. 0 software platform and the ALTERA Cyclone series EP1C6Q240C8N as the hardware platform. Matlab simulation verifies the correctness of the encoding results. This encoding scheme can be flexibly applied to systems of different code lengths.