摘要
数字电路逻辑图的校对是电路设计过程中的一个重要环节 ,全面的校对可在电路实现的早期发现、解决问题。本文总结了数字电路逻辑图设计、校对中所应注意的问题 ,提出了校图的原则和程序。
It's very important to verify the digital circuit schematics in the circuit designs.Problems may be found and resolved early on theimplementation of digital circuit by thorough verification.This paper summarizes the issues that should be pay attention to in the desing and verification of digital circuit schematics,then gives the principium and program on the verification of schematics.
出处
《航空计算技术》
2000年第2期26-28,共3页
Aeronautical Computing Technique