一种基于近似计时模型的嵌入式CPU仿真器

An Approximate Timing Simulator for Embedded CPUs

为了提高开发效率,嵌入式系统软硬件协同开发中,常使用快速的嵌入式系统功能仿真器进行软件开发。同时,嵌入式应用往往有实时性要求,所以模拟器有必要在开发中对软件性能进行评估。然而由于快速的功能仿真器强调"高效实现硬件功能、忽略与功能无关的硬件特性",故无法提供有参考价值的程序性能信息。针对上述问题,提出功能仿真框架,通过提出"采样计时"的方法,实现了一种近似计时的功能仿真器。上述仿真器不仅保持了功能仿真器快速运行的特性,而且能够以较小的误差计算出的程序运行所需的时钟周期。近似计时的仿真器已应用于轨道车辆嵌入式系统的开发中。

It is currently a common practice to simultaneously perform software and hardware design with functional simulators. Meanwhile, the real-time requirements suggest that timing information must be maintained by the simulator. Traditional functional simulators focus on ＂improving the level of hardware abstraction to gain high simulation speed＂, and therefor cannot give acceptable timing information. To solve this problem, we improved a leading-edge function simulation framework, SimSoC, and proposed a ＂sampled timing method＂ to construct an approximately timing simulation model for embedded CPUs in this work. The simulator adopted our techniques hit a balance of simulation speed and accuracy and has been used in a real design process for the embedded system in high-speed trains.