FPGA芯片的链结构LUT自测试方法研究

Study on Chain-based BIST Architecture of LUTs in FPGA

基于内建自测试(BIST)思想的FPGA测试方法利用被测芯片中的资源来构建测试所需的TPG或ORA,以减少测试对输入输出引脚和外部ATE的需求。传统的FPGA芯片BIST方法仅考虑自测试结构内被配置为CUT的资源,从而需要进行多次组测试来完成整个芯片的测试。在现有LUT自测试链结构的基础上,通过合理选择TPG的电路结构及测试配置,能够在相同测试开销下增加TPG部分的故障覆盖率,提高测试效率。

BIST-based FPGA test uses the resource in the chip under test to build the TPG or ORA to reduce the usage of I/O pins and ATE.In traditional BIST methods of FPGA,only the fault detection of the CUT of BIST architectures is considered and the chip needs to be reconfigured several time to change different parts into CUT.In order to improve the efficiency of a chain-based BIST method of LUTs in FPGA,this article tried to find more suitable architecture and testing configurations of TPG which can reach a higher fault coverage of the TPG part.