基于FPGA的SDH设备时钟芯片技术

Design of SDH Device Clock Chip Based on FPGA

介绍一种采用FPGA(现场可编程门阵列电路)实现SDH(同步数字体系)设备时钟芯片设计技术,硬件主要由1个FPGA和1个高精度温补时钟组成.通过该技术,可以在FPGA中实现需要专用芯片才能实现的时钟芯片各种功能,而且输入时钟数量对比专用芯片更加灵活,实现该功能的成本降低三分之一.该技术实现的时钟输出完全符合ITU-T G.813标准,可广泛应用于各种SDH设备中.

The paper focuses on the implementation of SDH （Synchronous Digital Hierarchy） equipment clock chip based on FPGA （Field Programmable Gate Array）. The hardware consists of FPGA and TCXO （Temperature Compensate X＇tal （crystal） Oscillator）. Through the technology introduced, the functions can fulfill used to be realized in ASIC （Application Specific Integrated Circuit）. The numbers of input clock is more flexible than ASIC and the cost is reduced by 33%. The output clock complies with ITU G.813 standard and can be widely applied in SDH devices.