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一种应用于非接触智能卡锁相环连续时钟电路

A PLL Based Continuous Clock Circuit in SmartCard
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摘要 本文针对13.56MHz非接触智能卡芯片(符合ISO/IEC14443 type A协议标准)特殊应用,实现一种基于锁相环结构的连续时钟电路。电路在载波存在或丢失情况下,均能提供稳定准确的时钟频率,连续时钟电路输出13.56MHz时钟,功耗60μA,面积为165X150μm2。芯片经过SMIC 0.18μm eFlash工艺流片验证,测试表明在协议规定的1.5A/m-7.5A/m场强范围,各种交互波形情况下,芯片均工作正常。 This paper designed a PLL based continuous clock circuit for the special application of contactless smartcard which follows the ISO/IEC 14443 type A protocol. The circuit can generate a stable and precise 13.56MHz clock signal even if the carrier clock disappeared provisionally. Current consumption is 60 μ A and area is 165 × 150 μ m^2. This chip was taped out in SMIC 0.18 μ m eFlash process successfully and the test result shows the chip works well under every condition in the protocol.
出处 《中国集成电路》 2014年第5期35-39,共5页 China lntegrated Circuit
关键词 智能卡 锁相环 连续时钟 Smart Card PLL Continuous Clock
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参考文献3

  • 1B.Razavi.模拟CMOS集成电路设计.西安交通大学出版社.2010版:447-464.
  • 2Moon-HoChoi,A 13.56MHz Radio Frequency Idemi- fication Transponder Analog Front End Using a Dynam- ically Enabled Digital Phase I,ocked Ix)op. Transactions on Electrical and Electronic 20-23,2010. Materials. Vol. 11,No. 1, pp.
  • 3J.Maneatis andM.Horowitz, Precise Delay Generation Using Coupled Oscillators, IEEE J.Solid-State Circuit, vol.28,no.12,pp.1273-1282, 1993.

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