一种基于PC机的高速16位并行数据采集接口

High-Speed Data Acquisition System with 16-bit Parallel Interface Based on PC

介绍了一种在 PC机上实现的高速 16位并行数据采集接口。该接口由高速光电隔离电路 ,双端口 FIFO存储缓冲器电路及由 FPGA芯片构成的计算机接口逻辑与控制电路等组成。该接口电路将终端显示处理系统与前端数据处理系统通过光电耦合器隔离开来 ,避免了它们之间的相互干扰 ,较好地解决了 16位并行数据高速传输中存在的电磁干扰问题和大数据量实时有效传输问题。采用现场可编程门阵列 FPGA芯片 ,使硬件设计软件化 ,既实现了复杂逻辑功能设计 ,又减少了硬件电路规模 ,提高了系统的可靠性 ,在雷达、声纳等复杂系统中具有很好的应用价值。

A high speed data acquisition system with a 16 bit parallel interface based on PC is described. It is composed of a high speed opto isolator circuit,a first in/first out dual port memory buffer circuit and an interface circuit with a field programming gate array (FPGA) chip. This kind of interface circuit prevents interference between signal processor system and terminal display system, and solves the problems of electromagnetic interference (EMI) in data parallel transmission and high speed cache with a large number of data. With the FPGA chip, the system has such features of hardware design with software programming, implementation of complex logic circuit design in one chip, and reduction of hardware design size and high reliability. It can be used for complex systems, such as radar, sonar, etc.