基于FPGA的数字锁相环设计

Design of DPLL Based on FPGA

在介绍数字锁相环基本原理的基础上,给出了一种数字锁相环位同步提取电路设计方法,并通过设计仿真,验证了设计的正确性。

This paper introduces the design of DPLL clock recovery circuit, and gives a brief introduction to the principle of DPLL. Uses Verilog language to design the main modules of DPLL. Finally it gives the performance analyzing, and validate correctness of this design.