基于FPGA和有限状态机的守时系统设计

Design of Time Keeping Circuit Based on FPGA and FSM

通过对现阶段守时系统实际应用情况和技术特点的分析,提出了一种新的守时系统设计方案,设计了一个基于FPGA和有限状态机的守时系统;采用恒温晶振组成本地时钟,与GPS/北斗时钟源共同作为系统的输入信号,利用FPGA设计守时系统的基本电路和有限状态机,并对调频调相部分和外部D/A转换电路进行控制,实现本地时钟与时钟源完全同频同相输出,从而快速获得高精度的时间基准,并能在GPS/北斗失锁后对时钟源信号进行保持,实现通信系统的时间同步。

Through the analysis of the present stage punctual system＇s practical application situation and technical characteristic, to pro- pose a new designing program of the time keeping system and design a time keeping system based on FPGA and the finite state machine. U- sing the oven controlled crystal oscillator as the local clock and the input signals of the system together with GPS/beidou. FPGA is used to design the basic circuit and the finite state machine of the time keeping system and to control the two parts of frequency modulation and phase modulation and the external D/A converter circuit, then achieves local clock with the clock source to output the same frequency and phase completely, thus obtains the high accuracy time base quickly. It can keep the clock source signal after GPS/beidou loses lock to achieve time synchronization of the communication system.