VHDL表达式的可综合语法检查器

Syntax Checker for Synthesizable Subset of VHDL Expressions

VHDL的综合问题是当前 EDA研究的一个重要课题 .针对 VHDL复杂的语法结构 ,尤其是表达式的多样性 ,给出一个表达式的可综合语法检查器 .通过改变 VHDL表达式的产生式来解决在语法分析时遇到的二义性问题 .最后给出表达式主要的产生式及测试结果 .

This paper presented a syntax checker for synthesizable subset of VHDL expressions to work out the difficulties brought by complex VHDL grammar, especially by the flexibility of expressions. By changing grammar rules the checker eliminates the ambiguities of VHDL expressions. The expression grammar rules and descriptions of test result were provided.