一种用于高速逻辑电路综合优化的新算法

Modified Retiming for the Timing Optimization of High Speed Logic Circuits

提出了一种改进时序重排算法 ,使时序重排可以更有效地与其他组合优化算法结合起来 ,共同提高同步时序电路的速度 .在各种不同的测试电路上得到的实验结果显示 ,这种算法在与其他组合优化方法的结合上 ,较以往的时序重排算法有很大的改进 .

Retiming is an effective technique to optimize the performance of synchronous sequential circuits. This paper proposed a new algorithm of retiming which can be combined well with other combinational optimization methods to speed up logic circuits. The experimental results from a variety of sequential benchmark circuits demonstrate a significant improvement over conventional retiming algorithms when combined with other combinational optimization methods.