从Verilog到VHDL的翻译器VtoV的设计与实现

Design and Implementation of the Translator of Verilog HDL to VHDL——VtoV

研究硬件描述语言 Verilog和 VHDL共有的语言特性 ,研制 SUN SPARC2工作站环境下的翻译系统 .在 SUN SPARC2工作站平台上使用 C++提取出了一组通用的硬件数据结构 ,可以进行代码重用 .在 SUN SPARC2工作站上设计和实现了一个从硬件描述语言 Verilog到 VHDL的翻译器 Vto V.该翻译器能够实现从 Verilog的行为子集到VHDL的转换 .

The common linguistic properties of Verilog HDL and VHDL are studied and a translating system between them in the workstation environment SUN SPARC2 is developed. The hardware generic data structure of C++ library is extracted in the workstation platform SUN SPARC2, and it can be reused. The translator for Verilog HDL to VHDL——VtoV is realized on SUN SPARC2.