基于FPGA的FIR滤波器设计方案优化

Optimized Scheme for Design of FIR Filter Based on FPGA

在介绍有限冲激响应(FIR)数字滤波器的理论基础上,提出了一种基于FPGA的16阶FIR低通数字滤波器的实现方案。该滤波器设计采用运算效率高的分布式算法结构,较好地解决了传统乘法累加结构运算速度低的不足。为节省硬件资源,设计中采取了分割查找表和偏移二进制数字编码技术,将所占ROM的大小由2LN减小到L/2(2N/2。最后给出了ModelSim下的仿真结果并对误差进行了分析,验证了该设计的正确性。

An implementation scheme of 16 order low pass FIR （finite impulse response） digital filter based on FPGA is proposed based on the theory of FIR digital filter.The DA （Distributed Arithmetic） structure is used to design FIR digital filter.The DA structure has high efficiency operation performance and is superior to traditional multiplyaccumulate （MAC） structure.In order to save hardware resources,the techniques of lookup table segmentation and offset-binary coding are used,and thus the size of occupied ROM reduced from 2LN to L/2 （2N/2.Finally,the simulation result is given based on ModelSim and the error is analyzed.The research results show that the correctness of the proposed design method.