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二维DMesh网络中基于转弯模型的无死锁路由算法研究

On a novel turn-model based deadlock-free routing algorithm for two-dimensional DMesh networks
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摘要 路由算法对整个互连网络的性能有着至关重要的影响。二维DMesh网络有效地结合了Mesh网络以及高阶路由器的优势,降低了网络的拓扑直径和平均跳步数,为消息传输提供了更多的可选择路径。针对DMesh网络,设计了一种基于转弯模型的适应性无死锁路由算法,该算法为消息传输提供了更多的灵活性。当网络中负载率较高时,能够指导消息避开拥塞区域和热点路由器,降低等待时间,最终指导消息以更快的速度到达目的节点。对新提出的路由算法进行了路径多样性方面的分析,并对算法的无死锁性进行了严格的证明。仿真实验结果表明,与DMesh网络中传统的DXY路由算法相比,这种新的适应性路由算法有效地降低了平均延迟,增加了消息传输的灵活性,最终提高了整个网络的通信性能。 Routing algorithm plays an important role in performance of interconnection networks.The 2D DMesh network combines the advantages of both Mesh network and high-radix routers,which lowers down the diameter and average hops in the whole network,as well as providing many more optional paths for messages.In DMesh,this paper presents a novel adaptive deadlock-free routing algorithm based on turn model,which provides much more flexibility for message routing in the network.When the load rate is high,the proposed routing algorithm could efficiently guide messages to avoid the congested area and hotspot routers,which directly translates to lower waiting time,and ultimately cuts down the average latency of the whole network.This paper analyzes the routing diversity of the proposed algorithm,and gives also the formal proof for the aspect of deadlock freedom.Compared with the original DXY routing algorithm,the simulation results show that the proposed algorithm could perfectly cut down average latency,improve transmitting flexibility,and enhance the communicating performance of the whole network.
作者 王新玉
出处 《沈阳师范大学学报(自然科学版)》 CAS 2014年第2期242-247,共6页 Journal of Shenyang Normal University:Natural Science Edition
基金 国家自然科学基金资助项目(71002094)
关键词 互连网络 DMesh 转弯模型 DXY路由算法 适应性路由算法 interconnection network DMesh turn model DXY routing algorithm adaptive routing algorithm
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参考文献15

  • 1KIM J, BALFOUR J, DALLY W J. Flattened butterfly topology for on-chip networks [C] ff Proceedings of International Symposium on Microarchiteeture. Piscataway NJ IEEE Computer Society, 2007172 - 182.
  • 2FLICH J, BERTOZZI D. Designing network-on-chip architectures in the nanoscale era[M]. Boca Raton: Chapman and Hall/CRC, 2011.
  • 3欧阳一鸣,朱兵,梁华国,冯伟.基于对角互连网格拓扑结构的片上网络[J].计算机工程,2009,35(22):100-102. 被引量:5
  • 4XU Yi, ZHAO 13o, ZHANG Youtao, et al. Simple virtual channel allocation for high throughput and high frequency on-chip routers[C] // Proceedings of International Symposium on Computer Architecture. Piscataway NJ: IEEE Computer Society, 2010:1 - 11.
  • 5WANG Xinyu, XIANG Dong. Multi-mappifig meshes: a new communicating fabric for networks-on-chip[C]/// Proceedings of International Conference on Parallel and Distributed Systems. Piscataway NJ: IEEE Computer Society, 2010:438- 445.
  • 6SCOTT S, ABTS D, DALLY W. High-radix interprocessor communications system and method: U.S. Patent 8,184,626[P]. 2012- 05- 22.
  • 7DALLY W, TOWLES 13. Principles and practices of interconneetion networks [M]. San Francisco: Morgan Kaufmann, 2004.
  • 8YU Zhigang, XIANG Dong, WANG Xinyu. VCBR: virtual channel balanced routing in torus networks[C]/// Proceeding of International Conference on High Performance Computing and Communications. Piscataway NJ: IEEE Computer Society, 2013:1359 - 1365.
  • 9GROT B,WECKLER S W. Scalable On-Chip Interconnect Topologies[C] ffProceedings of 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects. New York: Institute of Electrical and Electronics Engineers Incorporation, 2008 : 1 - 11.
  • 10GROT B, HESTNESS J, KECKLER S, et al. Express cube topologies for on-- chip interconnects[C] ffProceedings of International Conference on of High Performance Computer Architecture. Piscataway NJ: IEEE Computer Society, 2009: 163 - 174.

二级参考文献52

  • 1顾华玺,刘增基,王琨,谢启明.Torus网络中分布式自适应路由算法[J].西安电子科技大学学报,2006,33(3):352-358. 被引量:11
  • 2马立伟,孙义和.片上网络拓朴优化:在离散平面上布局与布线[J].电子学报,2007,35(5):906-911. 被引量:8
  • 3Benini L, Micheli G D. Networks on Chips: ANew SoC Paradigm[J]. IEEE Computer, 2002, 35(1): 70-80.
  • 4Li Yanjing, Zhang Jie. An Augmented Concentrated Mesh Network On Chip[EB/OL]. (2007-07-25). http://www.stanford.edu.
  • 5Rantala V. Network on Chip Routing Algorithms[R]. TUCS Technical Rep.: 779, 2006-10.
  • 6Hu Jingcao. DyAD Smart Routing for Networks-on-chip[C]// Proc. of 2004 Design Automation Conference. SanDiego, USA: [s. n.], 2004.
  • 7Daly W J, Towles B. Route Packets, Not Wires: On-chip Interconnection Networks[C]//Proc. of 2001 Design Automation Conference. Las Vegas, USA: [s. n.], 2001.
  • 8Das D,De M,Sinha BP.A new network topology with multiple meshes.IEEE Trans.on Computers,1999.536-551.
  • 9Mejia1 A,Flich1 J,Duato1 J,Reinemo S-A,Skeie T.Segment-Based routing:An efficient fault-tolerant routing algorithm for meshes and Tori.In:Proc.of the IEEE Int'l Parallel & Distributed Processing Symp.2006.http://ieeexplore.ieee.org/xpls/ abs_all.jsp?arnumber=1639341
  • 10Decayeux C,Seme D.3D hexagonal network:Modeling,topological properties,addressing scheme,and optimal routing algorithm.IEEE Trans.on Parallel and Distributed Systems,2005.http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1490517

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