摘要
反投影算法是一种基于时域处理的雷达成像算法。针对该算法运算效率低、处理速度慢的问题,通过分析反投影算法的原理及其运算过程,提出一种算法并行化加速方法,即基于现场可编程门阵列,将算法中的反投影运算单元设计成专用的反投影运算硬件加速模块,并通过模块内的流水线处理及多个模块间的并行计算提高该算法的运算效率。运用该方法对2 048×4 096大小的目标网格点进行反投影成像,成像时间为139 s,平均单点成像时间是基于GPU加速方法的3倍,并且成像结果和计算机成像结果误差极小。实验结果表明,该并行化方法可有效提高反投影算法的运算效率。
The Back Projection(BP) algorithm is a radar imaging algorithm based on time-domain processing. Aiming at the low computing efficiency and slow processing speed of BP algorithm, this paper proposes a parallel method after analyzing its principle and operation process. It analyzes the parallelization feasibility of the BP algorithm, and designs a dedicated BP operation module based on Field Programmable Gate Array(FPGA). To achieve the parallelization of the algorithm water treatment within a module and parallel processing between modules are adopted to speed up computations. It consumes 139 s to complete the computing of 2 048×4 096 target grid points using this method. The average time for a single-point is 3 times faster than the method based on GPU, and the imaging quality is as good as the results of computer imaging. Experimental result shows that the parallel method can effectively improve the operation efficiency of the BP algorithm.
出处
《计算机工程》
CAS
CSCD
2014年第5期285-288,294,共5页
Computer Engineering
基金
国家自然科学基金资助项目(61176024
61006018)
高等学校博士学科点专项科研基金资助项目(20120091110029)
江苏高校优势学科建设工程基金资助项目
关键词
反投影算法
反投影运算模块
合成孔径雷达
批处理
并行化
现场可编程门阵列
Back Projection(BP) algorithm
BP calculation module
Synthetic Aperture Radar(SAR)
batch processing
parallelization
Field Programmable Gate Array(FPGA)