一种高速数据采集系统的设计与实现

High-speed Data Acquisition System Design and Hardware Implementation

设计并实现了一种基于乒乓操作的高速数据采集系统。该系统使用两片SDRAM,同时设计了一种全新的SDRAM控制器,以现场可编程逻辑门阵列作为核心平台,通过高速数据接口,将采集到的数据通过总线传输到处理模块进行后续处理,从而完成数据的采集和处理任务。通过FPGA软硬件平台验证表明,该系统各模块均工作正常,并达到吞吐率指标,可满足数据采集、数据缓冲和数据接口匹配的需求。

One high-speed data acquisition system based on table tennis operation has been designed. This system use two SDRAM chips with a new SDRAM controller,use field programmable gate array（ FPGA） as a key design platform of the whole system,use to build table tennis operation module,and then let the data collected transmit to the next processing modules,through a variety of high-speed data interface or bus,so as to complete the data acquisition and processing tasks. Some experiments and tests based on FPGA show each module in this system works well,and meets the throughput rate requirement,and has achieved the data acquisition,data buffering and data interface matching requirement.