基于FPGA的数字下变频设计与实现

Design of Digital Down Conversion based on FPGA

数字下变频是全数字解调器中的关键技术之一,其性能好坏直接决定解调器的工作性能。给出一种基于FPGA的数字下变频设计,详细介绍正交变换、CIC抽取滤波及根升余弦滚降FIR低通滤波器的原理设计,并可编程设置各个模块参数,自动生成及动态配置滤波器系数。该设计在Xilinx公司XC3S4000 FPGA芯片的硬件平台和ISE 9.2开发环境下,采用Verilog语言编程实现,经过实际通信系统验证,在全数字解调器中很好地完成了多载波、多速率信号的数字下变频处理功能,具有很强的灵活性、稳定性和可扩展性。

Digital Down Conversion （DDC） is one of the key technologies for digital demodulator, which performance directly determines the capability of the digital demodulator. In this paper, an DDC framework based on FPGA is proposed, and the design methods for each DDC modules are discussed in detail, which includes frequency mixing module, CIC filter and square root raised cos rolloff FIR filter. The design of DDC can realize programmed configuration of each module parameter, automatic generation and dynamic configuration of filer parameters. It is realized on XC3S4000 FPGA chip and ISE 9.2 software development, used Verilog Programing language. This de- sign completes digital down coversion of multi carrier and multi rate signals in the actual communication system verification.which has very strong stability, flexibility and scalability.