基于动态相位调整算法的高速采样系统设计

Design of a High Speed Sampling System Based on Dynamic Phase Modulation Algorithm

高速采样技术在雷达信号处理系统中至关重要。在使用多通道串行输出AD芯片进行采样时,AD芯片输出的时钟信号与串行数据信号在传输的过程中获得了不同程度的延时,导致关键路径的时序要求不能够得到满足。为了解决上述问题,提出了一种自适应动态相位调整算法,动态调整时钟和数据的相位关系使其能够在高速条件下正确匹配;设计了基于ADS6445模数转换芯片和Virtex-5 FPGA芯片的采样系统对算法进行验证,经系统测试该算法成功将时钟变化沿对准了数据窗中心位置,大幅度提高了系统采样的准确性和稳定性。经计算,系统的采样数据有效位达到11位以上,满足雷达信号处理对数据精度的高要求。

High speed sampling technology is extremely important in radar signal processing systems, somesystems employ multi-channel serial-output AD （Analog to Digital） chips to sample data, because the delays of clock signal and serial data signal are not equal during the transmission, the timing constraints ofcrucial paths couldn＇t be matched. To solve above-mentioned problem,this paper presents a self-adjustdynamic phase modulation algorithm which modulates the phase relationship between clock and data tomake sure they match correctly in high speed conditions. A sampling system based on ADS6445 analog todigital chip and Virtex-5 FPGA（Field Programmable Gate Array） chip is designed to validate the algorithm. Test shows the algorithm successfully matches the clock edge to the middle of data window and largely improves the stability and veracity of the system. The ENOB（Effect Number of Bits） of the system ishigher than 11,so the system completely meets the high data precision demand of radar signal processing.