摘要
A10 bit 250 MS/s current-steering digital-to-analog converter is presented. Only standard Vv core de- vices are available for the sake of simplicity and low cost. In order to meet the INL performance, a Monte Carlo model is built to analyze the impact of mismatch on integral nonlinearity （INL） yield with both end-point line and best-fit line. A formula is derived for the relationship oflNL and output impedance. The relation of dynamic range and output impedance is also discussed. The double eentroid layout is adopted for the current source array in order to mitigate the effect of electrical, process, and temperature gradient. An adapted current mirror is used to over- come the gate leakage of the current source array, which cannot be ignored in the 65 nm GP CMOS process. The digital-to-analog converter occupies 0.06 mm2, and consumes 2.5 mW from a single 1.0 V supply at 250 MS/s.
A10 bit 250 MS/s current-steering digital-to-analog converter is presented. Only standard Vv core de- vices are available for the sake of simplicity and low cost. In order to meet the INL performance, a Monte Carlo model is built to analyze the impact of mismatch on integral nonlinearity （INL） yield with both end-point line and best-fit line. A formula is derived for the relationship oflNL and output impedance. The relation of dynamic range and output impedance is also discussed. The double eentroid layout is adopted for the current source array in order to mitigate the effect of electrical, process, and temperature gradient. An adapted current mirror is used to over- come the gate leakage of the current source array, which cannot be ignored in the 65 nm GP CMOS process. The digital-to-analog converter occupies 0.06 mm2, and consumes 2.5 mW from a single 1.0 V supply at 250 MS/s.
基金
Project supported by the Doctoral Fund of Ministry of Education of China(No.20110071110014)
