基于Verilog HDL的FIR数字滤波器的优化设计与仿真

Optimization design and simulation of FIR digital filter based on Verilog HDL

对FIR数字滤波器基于Verilog HDL的实现进行了研究,在分布式算法的基础上进行了改进,设计了32阶常系数FIR滤波器。用Verilog硬件描述语言进行数字逻辑设计,使用Synopsys VCS作为仿真工具对设计进行仿真和验证,在Synopsys公司的Design Compiler下进行综合。结果表明,该设计既保证了运行速度又节省了芯片的面积,可以广泛应用于数字集成电路的设计中。

The realization of FIR digital filter based on Verilog HDL was studied and was improved on the basis of the dis-tributed algorithm. A 32-order constant coefficient FIR filter was designed. Verilog hardware description language was used for digital logic Design. The design was simulated and verified by taking Synopsys VCS as a simulation tool. It was synthesized with Design Compiler of Synopsys Company. The results show that the design can noy only ensure the running speed,but also save the area of the chip. It can be widely used in the design of digital integrated circuit.