基于OR1200的SoC设计软硬件协同仿真验证

Simulation and Co-verification of SoC Based on OR1200

介绍了基于OR1200开源处理器SoC设计的软硬件协同验证,以及软件仿真在FPGA开发板的验证。搭建以OR1200、WishBone总线、通用异步收发器、Advanced Debug Interface、JTAG等通用IP核构建硬件实例,利用GNU工具链开发系统的软件程序和串口测试程序,通过两个途径实现了软硬件协同仿真验证工作,在OR1K处理器专用仿真软件OR1Ksim下进行仿真。最终使用调试器远程调试功能,通过JTAG调试接口,将系统在FPGA开发板上实现软硬件协同验证。

This paper introduces a method for software and hardware co-simulation and co-verification of SoC based on OR1200. OR1200, WishBone, UART, Advanced Debug System and JTAG cores are used to build the hardware system. The GNU tool chains are used to develop programs, which are simulated with orl ksim. The coverification of hardware and software is achieved with simulation software on FPGA via JTAG.