MPEG-2视频解码的VHDL描述与验证

VHDL description and verification for MPEG-2 video decoder VLSI design

本文提出一种MPEG 2视频解码的硬件结构 ,并采用VHDL进行了描述。为实现MPEG 2视频的实时解码 ,本文针对时序控制、变长码解码、反量化、IDCT、运动补偿和输入输出控制等各部分都提出了相应的高性能的电路结构。验证和仿真的结果表明 :本文的设计可以完成相应的功能 ,能被用于实现MPEG 2MP @ML的实时解码芯片。

A VHDL description of MEPG 2 video decoder is present in this paper The description is used for design of MPEG 2 video decoder chip A number of novel circuits and architectures are introduced for implement sequence control,variable length decoder,inverse quantization,inverse DCT motion compensation and memory control Verification shows that the design functions correctly,and can implement the video decoding of MP @ ML MPEG 2 stream