基于有限状态机的数字同步重频分选器

Digital Synchronous Repetition Rate Separation on FSM

针对FPGA/CPLD芯片设计中常常会遇到脉宽识别的问题 ,根据实际工程设计了一种同步重频分选器 ,它在某些通讯系统中有极其重要的应用。主要介绍如何通过同步有限状态机来设计该数字重频分选器 ,结合CPLD芯片的设计 ,给出了它的具体设计思想 ,以及VHDL语言描述的有限状态机的源代码、逻辑综合。

A Synchronization repetition rate separation chip is established for engineering according to the question of pulse width recognition in design of FPGA/CPLD Chips. And is has significant application in some communication systems. This paper introduces the theory of synchronous repetition rate separation, presents source code program of finite-state machine (FSM) of VHSIC hardware description language (VHDL), the results of logic synthesize, and timing simulator.