硅基Ⅲ-Ⅴ族纳米线晶体管

Si-Based Ⅲ-Ⅴ Nanowire Transistors

硅基Ⅲ-Ⅴ族纳米线晶体管已经成为高速、低功耗纳米级器件的重要发展方向。首先,从气相-液相-固相生长和选择区域生长的角度,阐明了在硅衬底上无位错生长高晶体质量Ⅲ-Ⅴ族纳米线的机制。在此基础上,介绍了垂直结构和水平结构Ⅲ-Ⅴ族纳米线晶体管的制备方法。研究表明,垂直结构纳米线容易实现高密度生长,而水平结构纳米线有利于逻辑栅的制作。通过比较垂直生长、水平生长、衬底转移和自上而下纳米加工技术制备Ⅲ-Ⅴ族纳米线的工艺优缺点,为水平结构Ⅲ-Ⅴ族纳米线在硅衬底上的大面积异构集成及其器件的制作提供了新的解决方案。

The silicon-based Ⅲ-Ⅴ nanowire transistor becomes an important development direction for high-speed and low-power nanoscale devices. The growth mechanisms of high crystalline quality Ⅲ-Ⅴ nanowires on Si substrates without any mismatch dislocations are firstly presented from the aspects of the vapor-liquid-solid growth method and selective-area growth. And on this basis, the fabrication methods of the vertical and horizontal Ⅲ-Ⅴ nanowire transistors are introduced. The research results show that the vertical nanowires are easy to realize the high-density growth, while the horizontal nanowires are adapt to the logic-gate fabrication. The new solutions for the large-area heterogeneous integration of the horizontal Ⅲ-Ⅴ nanowire on silicon substrate and the fabrication of the devices are provided by the comparison of the advantages and disadvantages of the Ⅲ-Ⅴ nanowire fabrications with the vertical growth, horizontal growth, substrate transfer and top-down process approach.