摘要
采用SMIC 0.18μm CMOS工艺,设计了高速收发器中双模1:8/1:10解复用电路。解复用电路采用半速率结构,基于电流模式逻辑完成对2.5 Gb/s差分数据1:2解复用电路;基于交替反相的锁存器和反馈逻辑完成双模4/5时钟分频和占空比调节;通过适当的相位控制实现了由相位控制链、交替存储链和同步输出链构成的1:4/1:5模式可选的数字CMOS解复用电路;1:2与1:4/1:5解复用级联完成1:8/1:10串并转换。采用数模混合仿真方法对电路进行仿真,结果表明该电路能可靠工作。
A dual-mode 1：8/1：10 demultiplexing circuit used in high-speed transceiver is designed with SMIC 0.18μm CMOS technology. The demultiplexer is based on half-rate architecture, with 1：2 demultiplexing for 2.5 Gb/s differential data based on current mode logic, dual-mode 4/5 frequency division and duty-cycle adjustment based on alternate inversion latches, dual-mode 1： 4/1：5 digital demultiplexer consisting of phase control chain, alternate sample chain and synchronous output chain with appropriate phase control. The 1：2 and 1：4/1：5 demuhiplexer cascade for 1：8/1：10 deserialization. The proposed circuit is verified with digital/ analog mixed simulation method and the results show that the circuit can work reliably.
出处
《微型机与应用》
2014年第11期60-64,共5页
Microcomputer & Its Applications
基金
国家自然科学基金重点项目(61136002)
国家自然科学基金面上项目(61272120)
陕西省教育厅专项科研计划项目(2010JK817)
